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ML2280 데이터시트(PDF) 11 Page - Micro Linear Corporation |
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ML2280 데이터시트(HTML) 11 Page - Micro Linear Corporation |
11 / 20 page ML2280, ML2283 11 When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of 1/2 clock period is used for sample & hold settling through the selected MUX channels. The SAR status output goes high at this time to signal that a conversion is now in progress and the DI input is ignored. The DO output comes out of High impedance and provides a leading zero for this one clock period. When the conversion begins, the output of the comparator, which indicates whether the analog input is greater than or less than each successive voltage from the internal DAC, appears at the DO output on each falling edge of the clock. This data is the result of the conversion being shifted out (with MSB coming first) and can be read by external logic or µP immediately. After 8 clock periods, the conversion is completed. The SAR status line returns low to indicate this 1/2 clock cycle later. The serial data is always shifted out MSB first during the conversion. After the conversion has been completed, the data can be shifted out a second time with LSB first. The 2280 data is shifted out only once, MSB first. All internal registers are cleared when the CS input is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI input and DO output can be tied together and controlled through a bidirectional µP I/O bit with one connection. This is possible because the DI input is only latched in during the MUX addressing interval while the DO output is still in the high impedance state. REFERENCE The ML2280 and ML2283 are intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog inputs vary between very specific voltage limits and the reference voltage for the A/D converter must remain stable with time and temperature. For ratiometric applications, see the ML2281 and ML2284 which have a VREF input that can be tied to VCC. The voltage applied to the VREF/2 pin defines the voltage span of the analog input (the difference between VIN+ and VIN–) over which the 256 possible output codes apply. A full-scale conversion (an all 1s output code) will result when the voltage difference between a selected “+”input and “–” input is approximately twice the voltage at the VREF/2 pin. This internal gain of 2 from the applied reference to the full- scale input voltage allows biasing a low voltage reference diode from the 5VDC converter supply. To accommodate a 5V input span, only a 2.5V reference is required. The output code changes in accordance with the following equation: Output Code VV V IN IN REF = +− − 256 2 2 () () () / where the output code is the decimal equivalent of the 8-bit binary output (ranging from 0 to 255) and the term VREF/2 is the voltage to ground. The VREF/2 pin is the center point of a two resistor divider (each resistor is 10k W) connected from VCC to ground. Total ladder input resistance is the parallel combination of these two equal resist. As show in Figure 8, a reference diode requiring an external biasing resistor if its current requirements meet the indicated level. The minimum value of VREF/2 can be quite small (See Typical Performance Curves) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1LSB equals VREF/256). Figure 8. Reference Biasing ML2280 ML2283 10k Ω 5V 2.5V VREF/2 VCC VFULL-SCALE ≅ 5.0V NOTE: NO EXTERNAL BIASING RESISTOR NEENED IF: VZ < AND IZ min. < 10k Ω GND ML2280 ML2283 10k Ω 1.2V VREF/2 IZ VZ – + VCC 5V VFULL-SCALE ≅ 2.4V 10k Ω GND VCC 2 VCC/2 – VZ 5k Ω |
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