ML2252, ML2259

5

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC and Dynamic Performance Characteristics (Note 5)

Sample and Hold Acquisition

1/2

Clock Frequency

10

1460

kHz

Conversion Time

8.5

8.5 + 250ns

SNR

Signal to Noise Ratio

47

dB

of all nonfundamental components

THD

Total Harmonic Distortion

–60

dB

THD is sum 2, 3, 4, 5 harmonics

relative to fundamental

IMD

Intermodulation Distortion

–60

dB

FR

Frequency Response

0.1

dB

to 1kHz

Clock Duty Cycle

(Note 6)

40

60

%

End of Conversion Delay

1/2

1/2 + 250ns

Start Pulse Width

50

ns

Start Pulse Setup Time

Synchronous only, (Note 7)

40

ns

Address Latch Enable

50

ns

Pulse Width

Address Setup

0

ns

Address Hold

50

ns

Output Enable for DB0–DB7

100

ns

50

ns

Output Disable for DB0–DB7

100

ns

50

ns

Capacitance of Logic Input

5

pF

Capacitance of Logic Outputs

10

pF

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.

cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either

Note 4: Leakage current is measured with the clock not switching.

Note 6: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,

the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.

Note 7: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,

start conversion will have an uncertainty of one clock pulse.