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N01S830BAT22IT 데이터시트(PDF) 8 Page - ON Semiconductor |
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N01S830BAT22IT 데이터시트(HTML) 8 Page - ON Semiconductor |
8 / 13 page N01S830HA, N01S830BA http://onsemi.com 8 Figure 11. QUAD Read Mode Register Sequence (RDMR) C[1:0] = 05h Notes: CS Instruction 03 2 1 SCK C1 C0 H L MSB Mode Bits SIO[3:0] Write Mode Register (WRMR) This instruction provides the ability to write the mode register. The Write Mode Register operation is executed by driving CS low, then sending the WRMR instruction to the device. Immediately after the instruction, the data is driven to the device on the SO (SIO0-3) pin(s). To complete the operation, drive CS high to terminate the register write. Figure 12. SPI Write Mode Register Sequence CS Instruction SI 04 3 25 16 9 810 711 SCK 7 65 43 210 High−Z Mode Register Data In SO 00 0 00 1 0 12 13 14 15 0 Figure 13. DUAL Write Mode Register Sequence C[3:0] = 01h Notes: CS Instruction 03 2 1 SCK C3 C2 H L MSB Mode Bits SIO[1:0] 45 L H C1 C0 67 Figure 14. QUAD Write Mode Register Sequence CS Instruction 03 2 1 SCK C1 C0 H L C[1:0] = 01h Notes: MSB Mode Bits SIO[3:0] |
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