MC100EP196A

http://onsemi.com

10

Symbol

Characteristic

−40

°C

25

°C

85

°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Maximum Frequency

1.2

1.2

1.2

GHz

Propagation Delay

IN to Q; D(0−10) = 0

IN to Q; D(0−10) = 1023

EN to Q; D(0−10) = 0

D0 to CASCADE

1650

9500

1600

300

2050

11500

2150

420

2450

13500

2600

500

1800

10000

1800

350

2200

12200

2300

450

2600

14000

2800

550

1950

10800

2000

425

2350

13300

2500

525

2750

15800

3000

625

ps

Programmable Range

7850

9450

8200

10000

8850

10950

ps

Dt

Step Delay (Note 15)

D0 High

D1 High

D2 High

D3 High

D4 High

D5 High

D6 High

D7 High

D8 High

D9 High

13

27

44

90

130

312

590

1100

2250

4500

14

30

47

97

140

335

650

1180

2400

4800

41

100

145

360

690

1300

2650

5300

ps

NLIN

Non−Linearity (Note 21)

TBD

ps

Duty Cycle Skew (Note 16)

25

25

25

ps

Setup Time

D to LEN

D to IN (Note 17)

EN to IN (Note 18)

200

300

300

0

140

150

200

300

300

0

160

170

200

300

300

0

180

180

ps

Hold Time

LEN to D

IN to EN (Note 19)

200

400

60

250

200

400

100

280

200

400

80

300

ps

Release Time

EN to IN (Note 20)

SET MAX to LEN

SET MIN to LEN

150

400

350

−25

200

275

150

400

350

−75

250

200

150

400

350

−50

300

225

ps

RMS Random Clock Jitter @ 1.2 GHz

IN to Q; D(0:10) = 0 or SETMIN

IN to Q; D(0:10) = 1023 or SETMAX

0.86

0.89

1.16

1.09

1.12

1.02

ps

Input Voltage Swing

(Differential Configuration)

150

800

1200

150

800

1200

150

800

1200

mV

Output Rise/Fall Time @ 50 MHz

20−80% (Q)

20−80% (CASCADE)

85

100

100

140

135

200

85

110

110

150

135

200

95

130

125

170

155

220

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50

15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations

of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.

16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.

17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.

18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than

±75 mV to that IN/IN transition.

19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response

greater than

±75 mV to that IN/IN transition.

20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets

the specified IN to Q propagation delay and transition times.

21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.