TPS566250

SLVSCV3B – MARCH 2015 – REVISED JUNE 2015

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Feature Description (continued)

8.3.2 PWM Frequency and Adaptive On-Time Control

TPS566250 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

device runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the

on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,

8.3.3 Soft Start and Pre-Biased Soft Start

The TPS566250 has an internal 1 ms soft-start. When the EN pin becomes high, internal soft-start function

begins ramping up the reference voltage to the PWM comparator. The device contains a unique circuit to prevent

sinking current from the output during startup if the output is pre-biased. When the soft-start commands a voltage

higher than the pre-bias level (internal soft start becomes greater than feedback voltage FB), the controller slowly

activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It

then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D

is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that

from output pre-biased startup to normal mode operation.

8.3.4 Overcurrent Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The

switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This

voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.

If the measured voltage is above the voltage proportional to the current limit, the converter maintains the low-side

switch on until the measured voltage is below the voltage corresponding to the current limit at which time the

switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is

set to a fixed value and the current is monitored in the same manner. If the overcurrent condition exists for 7

consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output

current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the

counter is reset and the OCL limit is returned to the higher value.

There are some important considerations for valley overcurrent protection. The average load current is half the

peak-to-peak inductor current plus the valley overcurrent threshold during current limit. The output voltage falls

as the demanded load current exceeds the current limit. When the FB voltage becomes lower than 65% of the

target voltage, the UVP comparator detects it and the Hiccup sequence is initiated. After 10 µs detecting the UVP

voltage, device shuts down and re-starts after the hiccup time.

When the over current condition is removed, the output voltage returns to the regulated value.

8.3.5 UVLO Protection

Undervoltage lock out protection (UVLO) monitors the voltage of the VIN terminal. When the VIN voltage is lower

than UVLO threshold voltage, the device is shut off. This protection is non-latching.

8.3.6 Thermal Shutdown

TPS566250 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),

the device is shut off. This is non-latch protection.

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