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SM5165AV 데이터시트(PDF) 6 Page - Nippon Precision Circuits Inc |
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SM5165AV 데이터시트(HTML) 6 Page - Nippon Precision Circuits Inc |
6 / 10 page SM5165AV NIPPON PRECISION CIRCUITS—6 Latch select The last (23rd) data bit determines the shift register data latch. Swallow counter, main counter frequency divider data and DO output Bits 19 and 20 have no meaning. These bits should be set to 0. Bits 20 and 21 control the state of the DO output pin. The DO output polarity can be set by master-slice for either a passive or active filter. Input data example If the VCO output is (fVCO) trebled, the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH: comparator frequency (fR) × 3) is 25 kHz, then the comparator frequency divider ratio N is given by: Therefore, the swallow counter count is 4 (00100)2 and the main counter count is 314 (0000100111010)2. Bit 23 Latch 0 Reference frequency counter divider ratio data latch select 1 Swallow counter and main counter frequency divider ratio and DO output latch select Bit 21 Bit 22 DO output 00 High impedance 10 01 Normal operation 11 Main counter (13-bit : 32 to 8191) No meaning 12 345 678 9 10 11 12 13 14 15 16 17 MSB DATA 18 19 20 21 22 23 LSB 22 222 222 22 222 222 12 11 10 98 765 43 210 432 22 10 Swallow counter (5-bit : 0 to 31) Latch select bit. Setting "1" DO output select bits N f LO f CH ---------- f VCO 3 × f R 3 × ----------------------- 251.3 3 ⁄ 0.025 3 ⁄ -------------------- 10052 32 314 4 + × == = = = 12 345 678 9 10 11 12 13 14 15 16 17 MSB 18 19 20 21 22 23 LSB 22 222 222 22 222 222 12 11 10 98 765 43 210 432 22 10 00 001 001 11 010 001 0 00 011 1 Input Data Main counter (13-bit : 32 to 8191) No meaning Swallow counter (5-bit : 0 to 31) Latch select bit. Setting "1" DO output select bits |
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