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TMP75CID 데이터시트(PDF) 9 Page - Texas Instruments |
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TMP75CID 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 31 page Measured Temperature T HIGH T LOW Device ALERTPIN (ComparatorMode) POL=0 Device ALERTPIN (InterruptMode) POL=0 Device ALERTPIN (ComparatorMode) POL=1 Device ALERTPIN (InterruptMode) POL=1 Read Read Time Read TMP75C www.ti.com SBOS707B – APRIL 2014 – REVISED AUGUST 2014 7.3.2 Temperature Limits and Alert The temperature limits are stored in the TLOW and THIGH registers (Table 7 and Table 8) in the same format as the temperature result, and their values are compared to the temperature result on every conversion. The outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or an interrupt, and is set by the TM bit in the Configuration register (Table 6). In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits of the configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive number of conversions. The difference between the two limits acts as a hysteresis on the comparator output, and a fault counter prevents false alerts as a result of environmental noise. In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs. After the ALERT pin is cleared, this pin becomes active again only when temperature falls below TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation of any register. The cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so on. The ALERT pin is cleared also when the device is placed in shutdown mode (see Shutdown Mode for shutdown mode description). This action also clears the fault counter memory. The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in the various modes is illustrated in Figure 7. Figure 7. ALERT Pin Modes of Operation Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TMP75C |
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