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CS3842BGD14 데이터시트(PDF) 5 Page - ON Semiconductor |
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CS3842BGD14 데이터시트(HTML) 5 Page - ON Semiconductor |
5 / 8 page Figure 3: Oscillator Timing Network and parameters VREF OSC Gnd RT CT VOSC Internal Clock LARGE RT (≈10kΩ) VREF Internal Clock SMALL RT (≈700kΩ) 5 Figure 3: Oscillator Sawtooth Mode Triangular Mode Vupper Vlower tc td Figure 2: Timing Diagram for key CS-384XB parameters VCC IOUT VOUT Switch Current EA Output VOSC OSC RESET cycle tends to exceed the maximum allowed, to prevent transformer saturation in some power supplies, the inter- nal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components. Setting the Oscillator The oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source (Figure 3). During the discharge time, the internal clock signal blanks out the output to the Low state, thus provid- ing a user selected maximum duty cycle clamp. Charge and discharge times are determined by the general formulas: tc = RTCT ln td = RTCT ln Substituting in typical values for the parameters in the above formulas: VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA, then tc ≈ 0.5534RTCT td = RTCT ln The frequency and maximum duty cycle can be deter- mined from the Typical Performance Characteristics graphs. Grounding High peak currents associated with capacitive loads neces- sitate careful grounding techniques. Timing and bypass capacitors should be connected close to ground in a single point ground. The transistor and 5k Ω potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. ) 2.3 – 0.0083 RT 4.0 – 0.0083 RT ( ) VREF – Id RT –Vlower VREF – Id RT – Vupper ( ) VREF – Vlower VREF – Vupper ( |
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