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SM8750AV 데이터시트(PDF) 6 Page - Nippon Precision Circuits Inc |
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SM8750AV 데이터시트(HTML) 6 Page - Nippon Precision Circuits Inc |
6 / 10 page SM8750AV NIPPON PRECISION CIRCUITS—6 FUNCTIONAL DESCRIPTION Serial Interface The SM8750AV has a dedicated serial interface port over which data can be written and the various oper- ating modes can be controlled. The port address and bit configuration are shown in table 1, and the data bits are described in table 2. ×: Don’t care. Serial data comprising 16 bits is input with the LSB first. Valid data is read in on the 16th rising edge of the SCLK input. On the next SCLK falling edge, the SDATA N-channel open drain is turned ON and SDATA goes LOW, performing the function of an acknowledge signal. If 15 or less SCLK rising edge pulses occur during the interval when SENB is HIGH, the data received up to the point when SENB goes LOW is ignored and the internal port data is not updated. If 17 or more SCLK rising edge pulses occur, the received data is latched in the internal port on the 16th rising edge and the acknowledge signal is output on the next falling edge. The acknowledge signal is held constant until SENB goes LOW again. Table 1. Port address and bit configuration Bit number 15 (msb) 1 4 1 3 1 2 1 1 1 0 987654321 0 (lsb) Data Address TEST1 TEST0 CSDIS C S S P POLAR GMES F C G × L O W HIGH HIGH HIGH HIGH HIGH × Table 2. Data bit description Bit Description Default TEST[1:0] Test mode setting L O W:LO W (normal operation) CSDIS A uto-adjust disable L O W (enabled) C S A uto-adjust start L O W (wait) S P Sleep mode settings L O W (normal operation) POLAR D ATA edge settings for phase measurement P olarity setting for conver ter coefficient measurement LO W (falling edge) (1T discharge) GMES C o n ver ter coefficient measurement mode setting L O W (normal operation) FCG RDCLK pulsewidth auto-adjust mode Phase difference to voltage converter coefficient switching LO W (minimum pulsewidth) (maximum conver ter coefficient) Table 3. GMES and POLAR operating modes GMES POLAR Operating mode L O W L O W D ATA signal falling edge and RDCLK rising edge phase difference conversion L O W HIGH DATA signal rising edge and RDCLK r ising edge phase difference conversion HIGH L O W Output conver ter voltage for phase difference equivalent to −0.5T HIGH HIGH Output conver ter voltage for phase difference equivalent to +0.5T |
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