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STK672-400 데이터시트(PDF) 9 Page - ON Semiconductor |
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STK672-400 데이터시트(HTML) 9 Page - ON Semiconductor |
9 / 19 page STK672-400 No.A0751-9/19 Usage Notes 1. Input pins and functional overview [Input pins] Hybrid IC pin No. Symbol Function Pin type 19 Vref Current setting Input impedance: 200k Ω (typical) 10, 11, 13 MODE1, MODE2, MODE3 Excitation mode setting TTL level Schmitt input 12 CLK Phase switching clock (speed command) Same as the above 13 CWB Motor direction setting Same as the above 14 RESET System reset Same as the above 15 ENABLE Motor current off Same as the above 2. Input signal functions [CLK (Phase switching clock)] (1) Input frequency: DC to 50kHz (2) Minimum pulse width: 10 μs (3) Pulse width duty: 40 to 60% (4) Pin circuit type: TTL level Schmitt trigger input (5) A multi-stage noise exclusion circuit is included. (6) Function • M3:1 When M3 is 1:The excitation phase is advanced one step on each CLK signal rising edge. • M3:0 When M3 is 0:The excitation phase is advanced one step alternately on each CLK signal rising or falling edge. • Timing chart [CWB (Motor direction setting)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function • When CWB = 0: The motor turns in the clockwise direction • When CWB = 1: The motor turns in the counterclockwise direction (3) Note: The value of the CWB input must not be changed in the period from 7 μs before a CLK input rising or falling edge until 7 μs after that edge. [ENABLE (Forces the excitation drive outputs A, AB, B, and BB to the off state and selects the hybrid IC's internal state to be operating or hold)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function a) When ENABLE is 1: Normal operating state b) When ENABLE is 0: The motor current is turned off and the excitation drive output is turned off forcibly. At this time, the hybrid IC's system clock is stopped and the hybrid IC is not influenced by changes to any input pins other than the reset input. Excitation counter up/down CLK input System clock Phase excitation counter clock Control output timing Control output switching timing |
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