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54ABT273J-QML 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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54ABT273J-QML 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Pin Description Names D 0–D7 Data Inputs MR Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q 0–Q7 Data Outputs Truth Table Mode Select-Function Table Operating Mode Inputs Output MR CP D n Q n Reset (Clear) L X X L Load “1” H N hH Load “0” H N lL H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran- sition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran- sition X = Immaterial N = LOW-to-HIGH clock transition Logic Diagram Pin Assignment for DIP and Flatpack DS100205-1 Pin Assignment for LCC DS100205-2 DS100205-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 |
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