전자부품 데이터시트 검색엔진 |
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54AC299LCC 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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54AC299LCC 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
2 / 10 page Connection Diagrams (Continued) Pin Names Description CP Clock Pulse Input DS 0 Serial Data Input for Right Shift DS 7 Serial Data Input for Left Shift S 0,S1 Mode Select Inputs MR Asynchronous Master Reset OE 1,OE2 TRI-STATE Output Enable Inputs I/O 0– I/O7 Parallel Data Inputs or TRI-STATE Parallel Outputs Q 0,Q7 Serial Outputs Functional Description The ’AC/’ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform syn- chronous shift left, shift right, parallel load and hold opera- tions. The type of operation is determined by S 0 and S1,as shown in the Truth Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q 0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE 1 or OE2 disables the TRI-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S 0 and S1 in preparation for a parallel load operation. Truth Table Inputs Response MR S 1 S 0 CP L X X X Asynchronous Reset; Q 0–Q7 = LOW HHH N Parallel Load; I/O n → Qn HLH N Shift Right; DS 0 → Q0, Q 0 → Q1, etc. HH L N Shift Left, DS 7 → Q7, Q 7 → Q6, etc. H L L X Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition www.national.com 2 |
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