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SI597 데이터시트(PDF) 2 Page - Silicon Laboratories |
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SI597 데이터시트(HTML) 2 Page - Silicon Laboratories |
2 / 12 page Si597 2 Rev. 1.0 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage1 VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Supply Current IDD Output enabled LVPECL CML LVDS CMOS — — — — 120 110 100 90 135 120 110 100 mA mA mA mA Tristate mode — 60 75 mA Output Enable (OE)2 and Frequency Select (FS[1:0]) VIH 0.75 x VDD —— V VIL —— 0.5 V Operating Temperature Range TA –40 — 85 °C Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details. 2. OE pin includes an internal 17 k pullup resistor to V DD for output enable active high or a 17 k pull-down resistor to GND for output enable active low. See 3. "Ordering Information" on page 7. FS[1:0] includes internal 17 k pull-up to VDD. Table 2. VC Control Voltage Input Parameter Symbol Test Condition Min Typ Max Unit Control Voltage Tuning Slope1,2,3 KV 10 to 90% of VDD — — — — — 45 95 125 185 380 — — — — — ppm/V Control Voltage Linearity4 LVC BSL –5 ±1 +5 % Incremental –10 ±5 +10 % Modulation Bandwidth BW 9.3 10.0 10.7 kHz VC Input Impedance ZVC 500 — — k VC Input Capacitance CVC —50 — pF Nominal Control Voltage VCNOM @ fO —VDD/2 — V Control Voltage Tuning Range VC 0— VDD V Notes: 1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. KV variation is ±10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. |
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