전자부품 데이터시트 검색엔진 |
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SI7013EVB-UDP-M3L1 데이터시트(PDF) 3 Page - Silicon Laboratories |
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SI7013EVB-UDP-M3L1 데이터시트(HTML) 3 Page - Silicon Laboratories |
3 / 26 page Si7013EVB-UDP-M3L1 Rev. 0.2 3 2.1. Si7013EB—UDP Schematics and BOM Figure 4 shows the schematics of the Si7013EB-UDP port header card. VDD is connected to port pin 17 and GND is connected to port pin 16. This is the standardized location for power and ground on Silicon Laboratories UDP port headers. For port headers with only 8 port pins, the card can be offset with power and ground pins connecting properly and pins 1–8 of the Si7013EB-UDP overhanging. By default, the on board Si7013 (U1) connects SDA to port pin P1.5, SCL to P1.6 and CS to P1.7. There is an optional 6 pin flat flexible header connector J2 that can connect to an external “postage stamp” size evaluation board for the Si7013, Si7020, or Si7021. The “postage stamp” size evaluation boards and a 3-foot flat flexible cable are included with the Si7013USB-DONGLE evaluation kit and can be ordered separately. The optional postage stamp evaluation boards would have SDA connect to port pin 1.3 SCL to P1.4 and CS to P1.2. The BOM for the Si7013EB-UDP is shown in Table 1. Table 1. Si7013-UDP Bill of Materials Qty Ref Value Rating Tol Type PCB Footprint Mfr Part Number Mfr 1 C1 4.7uF 6.3 V ±20% X5R C0603 C0603X5R6R3-475M Venkel 3 C2, C3 0.1uF 0 V ±20% X7R C0402 C0402X7R160-104M Venkel 1 J2 FH12 FH12 CONN6N-FPC/ FFC-P0.5 FH12-6S-0.5SH(55) Hirose 1J3 CONN SOCKET 2x9 Socket SSW-109-02-F-D-RA Samtec 3 R1, R2, R13 10K 1/16 W ±5% ThickFilm R0402 CR0402-16W-1002J Venkel 2 R3, R4 2K 1/16 W ±5% ThickFilm R0402 CR0402-16W-2001J Venkel 10 R5, R6, R7, R8, R9, R10, R11, R12, R15, R16 0 1 A ThickFilm R0402 CR0402-16W-000 Venkel 1 R14 10K NTC thermistor R0603 NCP18XH103F03RB Murata 1 U1 Si7013 Humidity QFN24 4x4P0.5 Si7013-A-GM1 Silicon Labs |
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