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ADP1055 데이터시트(PDF) 34 Page - Analog Devices

부품명 ADP1055
상세설명  Digital Controller for Power Supply Applications with PMBus Interface
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ADP1055
Data Sheet
Rev. A | Page 34 of 140
PWM edges to be adapted on the fly. The ADT feature is activated
when the primary or secondary current (CS1 or CS2) falls below
the threshold programmed in Register 0xFE1E. The software
GUI allows the user to easily program the dead time values, and
it is recommended that the GUI be used for this purpose.
Figure 56. Adaptive Dead Time Window in the GUI
Before ADT is configured, the primary current threshold must
be programmed. Each individual PWM rising and falling edge
(t1 to t12) can then be programmed to have a specific dead time
offset at no load (zero current). This offset can be positive or
negative and is relative to the nominal edge position. When the
current is between zero and the threshold, the amount of dead time
is linearly adjusted in steps of 5 ns. The averaging period of the
CS1/CS2 current is selected using Register 0xFE1E[7], and the
speed of the dead time adjustment can also be programmed to
accommodate faster or slower adjustment in Register 0xFE1D[5:0].
For example, if the CS1 threshold is set to 2 A, t1 has a nominal
rising edge of 100 ns. If the ADT setting for t1 is 40 ns at no load,
t1 moves to 140 ns when the current is 0 A and to 120 ns when
the current is 1 A. Similarly, ADT can be applied in the negative
direction.
The ADT feature is useful in quasi resonant topologies where an
energy transfer occurs from the inductor (generally, from one or
more of the leakage inductance, magnetizing inductance, and
external inductance) to the capacitor (usually the drain-source
capacitance of the MOSFET power switch) for the purpose of
achieving zero voltage switching (ZVS).
Generally, the condition for ensuring ZVS is that the energy in
the inductor must exceed the energy in the capacitor. A
resonant transition occurs when energy is dumped from the
inductor to the capacitor (capacitor being charged with opposite
polarity voltage). At one point, there is close to 0 V across the
MOSFET, and at this point the power switch is turned on.
If this energy is not sufficient, the MOSFET turns on without
ZVS. In this case, ADT can be used to wait until the resonant
transition reaches its peak value so that a near ZVS turn-on is
achieved.
SR DELAY
The ADP1055 is well suited for dc-to-dc converters in isolated
topologies. Each time a PWM signal crosses the isolation barrier,
an additional propagation delay is added due to the isolating com-
ponents. The ADP1055 allows programming of an adjustable
delay (0 ns to 315 ns in steps of 5 ns) using Register 0xFE52[5:0].
This delay moves both SR1 and SR2 later in time with respect to
OUTA to OUTD to compensate for the added delay due to the
isolating components. In this way, the edges of all PWM outputs
can be aligned, and the SR delay can be applied separately as a
constant dead time.
CURRENT SHARING (ISHARE PIN)
The ADP1055 supports both analog current sharing and digital
current sharing. The ADP1055 can use either the CS1 current
information or the CS2 current information for current sharing.
Analog Current Sharing
Analog current sharing uses the internal current sensing
circuitry to provide a current reading to an external current
error amplifier. Therefore, an additional differential current
amplifier is not necessary.
The current reading from CS1 or CS2 can be output to the ISHARE
pin in the form of a digital bit stream, which is the output of the
current sense ADC (see Figure 57). The bit stream is proportional
to the current delivered by this unit to the load. By filtering this
digital bit stream using an external RC filter, the current infor-
mation is turned into an analog voltage that is proportional to
the current delivered by this unit to the load. This voltage can
be compared to the share bus voltage. If the unit is not supplying
enough current, an error signal can be applied to the VS± feed-
back point. This signal causes the unit to increase its output voltage
and, in turn, its current contribution to the load.
Figure 57. Analog Current Share Configuration
CURRENT
SENSE
ADC
SHARE
BUS
LPF
BIT STREAM
BIT STREAM
ISHARE
VOLTAGE
CURRENT
CS2–
CS2+


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