Si52112-B5/B6

Rev 1.2

5

Table 3. AC Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Crystal

Long-term Accuracy

—

—

250

ppm

Clock Input

CLKIN Duty Cycle

45

—

55

%

CLKIN Rise and Fall Times

0.5

—

4.0

V/ns

CLKIN Cycle-to-Cycle Jitter

—

—

250

ps

CLKIN Long Term Jitter

—

—

350

ps

Input High Voltage

XIN/CLKIN pin

2

—

V

Input Low Voltage

XIN/CLKIN pin

—

—

0.8

V

Input High Current

——

35

µA

Input Low Current

XIN/CLKIN pin, 0 < VIN <0.8

–35

—

—

µA

DIFF Clocks

Duty Cycle

Measured at 0 V differential

45

—

55

%

Skew

Measured at 0 V differential

—

—

60

ps

Output Frequency

VDD = 3.3 V

—

100

—

MHz

Frequency Accuracy

All output clocks

—

—

100

ppm

Slew Rate

Measured differentially from

±150 mV

0.6

—

4.0

V/ns

Cycle-to-Cycle Jitter

Measured at 0 V differential

—

28

70

ps

PCIe Gen 1 Pk-Pk Jitter,

Common Clock

PCIe Gen 1

—24

86

ps

PCIe Gen 2 Phase Jitter,

Common Clock

10 kHz < F < 1.5 MHz

—

1.35

3.0

ps

1.5 MHz < F < Nyquist

—

1.4

3.1

ps

PCIe Gen 3 Phase Jitter,

Common Clock

PLL BW of 2–4 or 2–5 MHz,

CDR = 10 MHz

—0.4

1.0

ps

PCIe Gen 3 Phase Jitter,

Separate Reference No Spread,

SRNS

PLL BW of 2–4 or 2–5 MHz,

CDR = 10 MHz

—

0.28

0.71

ps

PCIe Gen 4 Phase Jitter,

Common Clock

PLL BW of 2–4 or 2–5 MHz,

CDR = 10 MHz

—0.4

1.0

ps

Crossing Point Voltage at 0.7 V

Swing

300

—

550

mV

Voltage High

—

—

1.15

V

Voltage Low

–0.3

—

—

V

Notes:

1.

Visit www.pcisig.com for complete PCIe specifications.

2.

Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

3.

Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.