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SI53303 데이터시트(PDF) 10 Page - Silicon Laboratories |
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SI53303 데이터시트(HTML) 10 Page - Silicon Laboratories |
10 / 30 page Si53303 10 Preliminary Rev. 0.4 2. Functional Description The Si53303 is a low jitter, low skew dual 1:5 differential output buffer. The device has a universal input that accepts most common differential or LVCMOS input signals. Each output bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength. 2.1. Universal, Any-Format Input The Si53303 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 12 and 13 summarize the various input ac- and dc-coupling options supported by the device. Figures 3 and 4 show the recommended input clock termination options. Figure 1. Differential LVPECL, LVDS, CML AC-Coupled Input Termination Figure 2. LVCMOS DC-Coupled Input Termination Table 12. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No Yes Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 13. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V No Yes (3.3 V) Yes No Si533xx 0.1 uF 0.1 uF CLKx /CLKx 100 V DD S i533 xx V REF CL K x /C L K x 50 = 3.3V , 2.5V , 1.8V V DDO Rs CM O S Driv e r 0.1 u F N o te: V DDO and V DD m u st be at the sa m e vo ltage le ve l. |
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