CDCM7005ZVAT datasheet(10/52 Pages) TI1

부품명	CDCM7005ZVAT

상세설명	3.3-V High Performance Clock Synchronizer and Jitter Cleaner

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제조업체	TI1 [Texas Instruments]

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10 / 52 page

CDCM7005

SCAS793F – JUNE 2005 – REVISED JULY 2015

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Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

High-impedance state output current for PLL

IOZH LOCK

VO = 3.6 V (PD is set low)

45

65

µA

LOCK output(8)

High-impedance state output current for PLL

IOZL LOCK

VO = 0 V (PD is set low)

±5

µA

LOCK output(8)

VIT+

Positive input threshold voltage

VCC = min to max

VCC×0.55

V

VIT–

Negative input threshold voltage

VCC = min to max

VCC×0.35

V

PHASE DETECTOR

fCPmax

Maximum charge pump frequency

Default PFD pulse width delay

100

MHz

CHARGE PUMP

ICP

Charge pump sink/source current range (9)

VCP = 0.5 VCC_CP

±0.2

±3

mA

ICP3St

Charge pump 3-state current

0.5 V < VCP < VCC_CP – 0.5 V

10

nA

VCP = 0.5 VCC_CP, internal reference resistor, SPI

10%

default settings

ICPA

ICP absolute accuracy

VCP = 0.5 VCC_CP, external reference resistor 12 kΩ

5%

(1%) at I_REF_CP, SPI default settings

ICPM

Sink/source current matching

0.5 V < VCP < VCC_CP – 0.5 V, SPI default settings

2.5%

IVCPM

ICP vs VCP matching

0.5 V < VCP < VCC_CP – 0.5 V

5%

(8)

Lock output has an 80-k

Ω pulldown resistor.

(9)

Defined by SPI settings.

7.6 Timing Requirements

over recommended ranges of supply voltage, load and operating free air temperature

MIN

NOM

MAX

UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

fREF_IN

LVCMOS primary or secondary reference clock frequency(1) (2)

0

200

MHz

tr/ tf

Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC

4

ns

dutyREF

Duty cycle of PRI_REF or SEC_REF at VCC/2

40%

60%

VCXO_IN, VCXO_IN REQUIREMENTS

fVCXO_IN

VCXO clock frequency(3)

0

2200

MHz

tr/ tf

Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz(4)

3

ns

dutyVCXO

Duty cycle of VCXO clock

40%

60%

SPI/CONTROL REQUIREMENTS (see Figure 23)

fCTRL_CLK

CTRL_CLK frequency

20

MHz

tsu1

CTRL_DATA to CTRL_CLK setup time

10

ns

th2

CTRL_DATA to CTRL_CLK hold time

10

ns

t3

CTRL_CLK high duration

25

ns

t4

CTRL_CLK low duration

25

ns

tsu5

CTRL_LE to CTRL_CLK setup time

10

ns

tsu6

CTRL_CLK to CTRL_LE setup time

10

ns

t7

CTRL_LE pulse width

20

ns

tr/ tf

Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC

4

ns

PD, RESET, HOLD, REF_SEL REQUIREMENTS

tr / tf

Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC

4

ns

(1)

At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the

STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.

(2)

fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).

(3)

If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!

(4)

Use a square wave for lower frequencies (< 80 MHz).

10

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