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DLP3010FQK 데이터시트(PDF) 10 Page - Texas Instruments |
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DLP3010FQK 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 39 page DLP3010 DLPS051A – SEPTEMBER 2014 – REVISED APRIL 2015 www.ti.com Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA IIH High–level input current VDD = 1.95 V; VI = 1.95 V 100 nA LPSDR OUTPUT(10) VOH DC output high voltage IOH = –2 mA 0.8 × VDD V VOL DC output low voltage IOL = 2 mA 0.2 × VDD V CAPACITANCE Input capacitance LPSDR ƒ = 1 MHz 10 pF CIN Input capacitance SubLVDS ƒ = 1 MHz 10 pF COUT Output capacitance ƒ = 1 MHz 10 pF CRESET Reset group capacitance ƒ = 1 MHz; (720 × 160) micromirrors 200 220 pF (10) LPSDR specification is for pin LS_RDATA. 6.7 Timing Requirements Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. MIN NOM MAX UNIT LPSDR tr Rise slew rate(1) (30% to 80%) × VDD, Figure 3 1 3 V/ns tƒ Fall slew rate(1) (70% to 20%) × VDD, Figure 3 1 3 V/ns tr Rise slew rate(2) (20% to 80%) × VDD, Figure 3 0.25 V/ns tƒ Fall slew rate(2) (80% to 20%) × VDD, Figure 3 0.25 V/ns tc Cycle time LS_CLK, Figure 2 7.7 8.3 ns tW(H) Pulse duration LS_CLK 3.1 ns 50% to 50% reference points, Figure 2 high tW(L) Pulse duration LS_CLK 3.1 ns 50% to 50% reference points, Figure 2 low tsu Setup time LS_WDATA valid before LS_CLK ↑, Figure 2 1.5 ns th Hold time LS_WDATA valid after LS_CLK ↑, Figure 2 1.5 ns tWINDOW Window time(1)(3) Setup time + Hold time, Figure 2 3 ns For each 0.25 V/ns reduction in slew rate below 0.35 ns tDERATING Window time derating(1)(3) 1 V/ns, Figure 5 SubLVDS tr Rise slew rate 20% to 80% reference points, Figure 4 0.7 1 V/ns tƒ Fall slew rate 80% to 20% reference points, Figure 4 0.7 1 V/ns tc Cycle time DCLK, Figure 6 1.79 1.85 ns tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6 0.79 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6 0.79 ns D(0:3) valid before tsu Setup time DCLK ↑ or DCLK ↓, Figure 6 D(0:3) valid after th Hold time DCLK ↑ or DCLK ↓, Figure 6 tWINDOW Window time Setup time + Hold time, Figure 6, Figure 7 0.3 ns tLVDS- Power-up receiver(4) 2000 ns ENABLE+REFGEN (1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3. (2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3. (3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. (4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DLP3010 |
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