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전자부품 데이터시트 검색엔진 |
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DLP4500NIRFQD 데이터시트(PDF) 9 Page - Texas Instruments |
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DLP4500NIRFQD 데이터시트(HTML) 9 Page - Texas Instruments |
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9 / 58 page  DLP4500NIR www.ti.com DLPS032A – FEBRUARY 2014 – REVISED JANUARY 2016 Connector Pins for FQD PIN PACKAGE NET INTERNAL TYPE SIGNAL DATA RATE (1) DESCRIPTION LENGTH (mm) TERMINATION NAME NO. (2) DATA INPUTS DATA(0) A1 Input LVCMOS DDR none Input data bus, bit 0, LSB 3.77 DATA(1) A2 Input LVCMOS DDR none Input data bus, bit 1 3.77 DATA(2) A3 Input LVCMOS DDR none Input data bus, bit 2 3.73 DATA(3) A4 Input LVCMOS DDR none Input data bus, bit 3 3.74 DATA(4) B1 Input LVCMOS DDR none Input data bus, bit 4 3.79 DATA(5) B3 Input LVCMOS DDR none Input data bus, bit 5 3.75 DATA(6) C1 Input LVCMOS DDR none Input data bus, bit 6 3.72 DATA(7) C3 Input LVCMOS DDR none Input data bus, bit 7 3.75 DATA(8) C4 Input LVCMOS DDR none Input data bus, bit 8 3.78 DATA(9) D1 Input LVCMOS DDR none Input data bus, bit 9 3.75 DATA(10) D4 Input LVCMOS DDR none Input data bus, bit 10 3.77 DATA(11) E1 Input LVCMOS DDR none Input data bus, bit 11 3.75 DATA(12) E4 Input LVCMOS DDR none Input data bus, bit 12 3.71 DATA(13) F1 Input LVCMOS DDR none Input data bus, bit 13 3.76 DATA(14) F3 Input LVCMOS DDR none Input data bus, bit 14 3.73 DATA(15) G1 Input LVCMOS DDR none Input data bus, bit 15 3.72 DATA(16) G2 Input LVCMOS DDR none Input data bus, bit 16 3.77 DATA(17) G4 Input LVCMOS DDR none Input data bus, bit 17 3.73 DATA(18) H1 Input LVCMOS DDR none Input data bus, bit 18 3.74 DATA(19) H2 Input LVCMOS DDR none Input data bus, bit 19 3.76 DATA(20) H4 Input LVCMOS DDR none Input data bus, bit 20 3.70 DATA(21) J1 Input LVCMOS DDR none Input data bus, bit 21 3.77 DATA(22) J3 Input LVCMOS DDR none Input data bus, bit 22 3.76 DATA(23) J4 Input LVCMOS DDR none Input data bus, bit 23, MSB 3.77 DCLK K1 Input LVCMOS DDR none Input data bus clock 3.74 DATA CONTROL INPUTS LOADB K2 Input LVCMOS DDR none Parallel-data load enable 3.74 TRC K4 Input LVCMOS DDR none Input-data toggle rate control 4.70 SCTRL K3 Input LVCMOS DDR none Serial-control bus 3.75 Stepped address-control serial- 3.77 SAC_BUS C20 Input LVCMOS — none bus data Stepped address-control serial- 1.49 SAC_CLK C22 Input LVCMOS — none bus clock MIRROR RESET CONTROL INPUTS DRC_BUS B21 Input LVCMOS — none DMD reset-control serial bus 3.73 Active-low output enable signal 3.74 DRC_OE A20 Input LVCMOS — none for internal DMD reset driver circuitry Strobe signal for DMD reset- 3.73 DRC_STROBE A22 Input LVCMOS — none control inputs (1) (a) DDR = Double data rate (b) SDR = Single data rate (c) Refer to Timing Requirements for specifications and relationships. (2) Net trace lengths inside the package: (a) Relative dielectric constant for the FQD ceramic package is 9.8. (b) Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns. (c) Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLP4500NIR |
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