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DLP5500AFYA 데이터시트(PDF) 8 Page - Texas Instruments |
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DLP5500AFYA 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 46 page DLP5500 DLPS013F – APRIL 2010 – REVISED MAY 2015 www.ti.com 8.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLY VOLTAGES(1) (2) VCC Supply voltage for LVCMOS core logic 3.15 3.3 3.45 V VCCI Supply voltage for LVDS receivers 3.15 3.3 3.45 V VCC2 Mirror electrode and HVCMOS supply voltage 8.25 8.5 8.75 V |VCCI–VCC| Supply voltage delta (absolute value) (3) 0.3 V VMBRST Micromirror clocking pulse voltages -27 26.5 V LVCMOS PINS VIH High level Input voltage (4) 1.7 2.5 VCC + 0.15 V VIL Low level Input voltage(4) – 0.3 0.7 V IOH High level output current at VOH = 2.4 V –20 mA IOL Low level output current at VOL = 0.4 V 15 mA TPWRDNZ PWRDNZ pulse width(5) 10 ns SCP INTERFACE ƒclock SCP clock frequency(6) 500 kHz tSCP_SKEW Time between valid SCPDI and rising edge of SCPCLK(7) –800 800 ns tSCP_DELAY Time between valid SCPDO and rising edge of SCPCLK (7) 700 ns tSCP_BYTE_INTERVAL Time between consecutive bytes 1 µs tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK 30 ns tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 µs tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tri-state) 1.5 ns ƒclock SCP circuit clock oscillator frequency (8) 9.6 11.1 MHz (1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected. (2) VOFFSET supply transients must fall within specified max voltages. (3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. (4) Tester Conditions for VIH and VIL: Frequency = 60MHz. Maximum Rise Time = 2.5 ns at (20% to 80%) Frequency = 60MHz. Maximum Fall Time = 2.5 ns at (80% to 20%) (5) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin. (6) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK. (7) Refer to Figure 3. (8) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required. 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLP5500 |
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