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DLPA2005ERSLR 데이터시트(PDF) 10 Page - Texas Instruments |
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DLPA2005ERSLR 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 55 page tCSCR tCDS tCDH tCFDO tCFCS tCSZ HiZ HiZ SPI_CSZ (SS) SPI_CLK (SCLK) SPI_DIN (MOSI) SPI_DOUT (MISO) tiS tiH tCLKL tCLKH DLPA2005 DLPS047B – SEPTEMBER 2014 – REVISED OCTOBER 2015 www.ti.com 6.6 Data Transmission Timing Requirements VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted) MIN TYP MAX UNIT ƒCLK Serial clock frequency 0 36 MHz tCLKL Pulse width low, SPI_CLK, 50% level 10 ns tCLKH Pulse width high, SPI_CLK, 50% level 10 ns tt Transition time, 20% to 80% level, all signals 0.2 4 ns tCSCR SPI_CSZ falling to SPI_CLK rising, 50% level 8 ns tCFCS SPI_CLK falling to SPI_CSZ rising, 50% level 1 ns tCDS SPI_DIN data setup time, 50% level 7 ns tCDH SPI_DIN data hold time, 50% level 6 ns tiS SPI_DOUT data setup time(1)), 50% level 10 ns tiH SPI_DOUT data hold time (1), 50% level 0 ns tCFDO SPI_CLK falling to SPI_DOUT data valid, 50% level 13 ns tCSZ SPI_CSZ rising to SPI_DOUT HiZ 6 ns (1) The DLPC3430/DLPC3435 processors send and receive data on the falling edge of the clock. Figure 1. SPI Timing Diagram 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DLPA2005 |
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