TS3006ITD833T datasheet(3/10 Pages) SILABS

부품명	TS3006ITD833T

상세설명	Single Resistor Sets Output Frequency

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TS3006

TS3006 Rev. 1.0

Page 3

ELECTRICAL CHARACTERISTICS

VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C

unless otherwise noted. See Note 1.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

VDD

1.55

5.25

V

Supply Current

IDD

1.9

2.4

µA

-40°C

≤ T

A ≤ 85°C

2.7

FOUT Period

tFOUT

39

40.1

41.2

µs

-40°C

≤ T

A ≤ 85°C

38

42

FOUT Period Line

Regulation

∆t

FOUT/V

1.55V

≤ V

DD ≤ 5.25V

0.17

%/V

FOUT Duty cycle

49

51

%

FOUT Period

Temperature

Coefficient

∆t

FOUT/∆T

0.02

%/°C

UVLO Hysteresis

VUVLO

(VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE)

150

250

mV

FOUT Rise Time

tRISE

See Note 2, CL = 15pF

10

ns

FOUT Fall Time

tFALL

See Note 2, CL = 15pF

10

ns

FOUT Jitter

See Note 3

0.001

%

RSET Pin Voltage

V(RSET)

0.3

V

Maximum Oscillator

Frequency

Fosc

RSET= 360K

300

kHz

High Level Output

Voltage, FOUT

VDD - VOH

IOH = 1mA

160

mV

Low Level Output

Voltage, FOUT

VOL

IOL = 1mA

140

mV

Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.

Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based

on lab bench characterization and is not tested in production.

Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench

characterization and is not tested in production.

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