TS7003

Page 4

TS7003 Rev. 1.0

TIMING SPECIFICATIONS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Period

208

ns

SCLK Pulse-Width High

83

ns

SCLK Pulse-Width Low

83

ns

CS Fall to SCLK Rise Setup

45

ns

SCLK Rise to CS Rise Hold

0

ns

SCLK Rise to CS Fall Ignore

45

ns

CS Rise to SCLK Rise Ignore

45

ns

SCLK Rise to DOUT Hold

13

ns

SCLK Rise to DOUT Valid

100

ns

CS Rise to DOUT Disable

13

85

ns

CS Fall to DOUT Enable

85

ns

CS Pulse-Width High

100

ns

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been

calibrated.

Note 3: Internal reference, offset, and reference errors nulled.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA because of

production test limitations.

Characteristics.