전자부품 데이터시트 검색엔진 |
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74F182SJ 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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74F182SJ 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL Cn Carry Input 1020 20 mA b12 mA G0 G2 Carry Generate Inputs (Active LOW) 10140 20 mA b84 mA G1 Carry Generate Input (Active LOW) 10160 20 mA b96 mA G3 Carry Generate Input (Active LOW) 1080 20 mA b48 mA P0 P1 Carry Propagate Inputs (Active LOW) 1080 20 mA b48 mA P2 Carry Propagate Input (Active LOW) 1060 20 mA b36 mA P3 Carry Propagate Input (Active LOW) 1040 20 mA b24 mA CnaxbCnaz Carry Outputs 50333 b 1 mA20 mA G Carry Generate Output (Active LOW) 50333 b 1 mA20 mA P Carry Propagate Output (Active LOW) 50333 b 1 mA20 mA Functional Description The ’F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate (P0–P3) and Carry Generate (G0–G3) signals and an Active HIGH Carry input (Cn) and provides anticipated Active HIGH carries (Cn a x Cnay Cnaz) across four groups of binary adders The ’F182 also has Active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead The logic equations provided at the outputs are Cnax e G0 a P0Cn Cnay e G1 a P1G0 a P1P0Cn Cnaz e G2 a P2G1 a P2P1G0 a P2P1P0Cn G e G3 a P3G2 a P3P2G1 a P3P2P1G0 P e P2P2P1P0 Also the ’F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode The connections (Figure 1) to and from the ALU to the carry lookahead gen- erator are identical in both cases Carries are rippled be- tween lookahead blocks The critical speed path follows the circled numbers There are several possible arrangements for the carry interconnects but all achieve about the same speed A 28-bit ALU is formed by dropping the last ’F181 or ’F381 TLF9492 – 5 FIGURE 1 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs ALUs may be either ’F181 or ’F381 2 |
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유사한 설명 - 74F182SJ |
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