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SN74HC125DBR 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 SN74HC125DBR
상세설명  Quadruple Bus Buffer Gates
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홈페이지  http://www.ti.com
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SN74HC125DBR 데이터시트(HTML) 4 Page - Texas Instruments

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SN54HC125
SN74HC125
SCLS104E – AUGUST 1984 – REVISED DECEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
7
V
IIK
Input clamp current(2)
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
Tj
Junction temperature
–65
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Electrostatic
V(ESD)
V
discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1).
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 6 V
4.2
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 6 V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
1000
∆t/∆v
Input transition rise and fall time
VCC = 4.5 V
500
ns
VCC = 6 V
400
SN54HC125
–55
125
TA
Operating free-air temperature
°C
SN74HC125
–40
85
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC1G06
PW
THERMAL METRIC(1)
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SOP)
UNIT
(TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
86
96
80
76
113
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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Copyright © 1984–2015, Texas Instruments Incorporated
Product Folder Links: SN54HC125 SN74HC125


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