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SN74HC125PWRE4 데이터시트(PDF) 10 Page - Texas Instruments |
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SN74HC125PWRE4 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 28 page 1 1OE 2 1A 1Y 3 4 2OE 5 2A 2Y 6 10 3OE 9 3A 3Y 8 13 4OE 12 4A 4Y 11 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. SN54HC125 SN74HC125 SCLS104E – AUGUST 1984 – REVISED DECEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The SNx4HC125 offers 4 independent gate buffers capable of sinking or sourcing 6 mA at 5-V VCC. Each buffer also integrates a 3-state output, or high impedance output. To enable the device's 3-state output, set the corresponding OE input to a HIGH logic level. Major benefits of using HC logic include both the technology's flexibility of input VCC (2 V to 6 V) and high- speed capability (11 ns typical tpd). 8.2 Functional Block Diagram 8.3 Feature Description The 3-state outputs enable design choices such as connecting multiple outputs together, as long as the 3-state controls are used correctly. In a typical example, without 3-state outputs, if two outputs were connected to the same input on an adjacent system, and each output was trying to drive a different logic level (one HIGH, one LOW), the device could short-circuit and become damaged. With 3-state output functionality, the outputs can be configured so that when one output is driving an output signal, the others are set to high impedance and prevent any damage to the device. 8.4 Device Functional Modes Table 1 lists the functional modes of the SNx4HC125. Table 1. Function Table INPUTS OUTPUT Y OE A L H H L L L H X Z 10 Submit Documentation Feedback Copyright © 1984–2015, Texas Instruments Incorporated Product Folder Links: SN54HC125 SN74HC125 |
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