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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Q67101-H6789 데이터시트(PDF) 69 Page - Siemens Semiconductor Group |
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Q67101-H6789 데이터시트(HTML) 69 Page - Siemens Semiconductor Group |
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69 / 272 page  SAB 82532/SAF 82532 Asynchronous Serial Mode Semiconductor Group 69 07.96 6.2 Data Reception 6.2.1 Operating Modes The ESCC2 offers the flexibility to combine clock modes, data encoding and data sampling in many different ways. However, only definite combinations make sense and are recommended for correct operation: Asynchronous Mode Prerequisites: • Bit clock rate 16 selected (CCR1:BCR = ‘1’) • Clock mode 0, 1, 3b, 4, or 7b selected • NRZ data encoding The receiver which operates with a clock rate equal to 16 times the nominal data bit rate, synchronizes itself to each character by detecting and verifying the start bit. Since character length, parity and stop bit length is known, the ensuing valid bits are sampled. Oversampling (3 samples) around the nominal bit center in conjunction with majority decision is provided for every received bit (including start bit). The synchronization lasts for one character, the next incoming character causes a new synchronization to be performed. As a result, the demand for high clock accuracy is reduced. Two communication stations using the asynchronous procedure are clocked independently, their clocks need not be in phase or locked to exactly the same frequency but, in fact, may differ from one another within a certain range. Isochronous Mode Prerequisites: • Bit clock rate 1 selected (CCR1:BCR = ‘0’) • Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1 or Manchester encoding. The isochronous mode uses the asynchronous character format. However, each data bit is only sampled once (no oversampling). In clock modes 0 and 1, the input clock has to be externally phase locked to the data stream. This mode allows much higher transfer rates. Clock modes 3b, 4 and 7b are not recommended due to difficulties with bit synchronization when using the internal baud rate generator. In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct synchronization of the DPLL is achieved if there are enough edges within the data stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester) is used. |
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