Theory of Operation

TLF6000 – 4

FIGURE 2

Trigger Operation

The block diagram of the CD4538B is shown in

Figure 1

with circuit operation following

As shown in

Figures 1 and 2 before an input trigger occurs

the monostable is in the quiescent state with the Q output

nized which turns on comparator C1 and N-Channel tran-

parator C1 changes state and transistor N1 turns off Com-

parator C1 then turns off while at the same time comparator

es state causing the output latch to reset (Q goes low) while

at the same time disabling comparator C2 This ends the

timing cycle with the monostable in the quiescent state

waiting for the next trigger

A valid trigger is also recognized when trigger input B goes

be zero Both comparators are ‘‘off’’ with the total device

current due only to reverse junction leakages An added

feature of the CD4538B is that the output latch is set

via the input trigger without regard to the capacitor voltage

Thus propagation delay from trigger to Q is independent of

Retrigger Operation

returned to the quiescent (zero) state Any retrigger after

the timing node voltage at pin 2 or 14 has begun to rise from

crease in output pulse width T When a valid retrigger is

Q output will remain high until time T after the last valid

retrigger

Reset Operation

The CD4538B may be reset during the generation of the

output pulse In the reset mode of operation an input pulse

will clear and then be ready to accept another pulse If the

inhibited and the Q and Q outputs of the output latch will not

change Since the Q output is reset when an input low level

significantly shorter than the minimum pulse width specifica-

tion

5