AD6672

Data Sheet

Rev. C | Page 2 of 30

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

ADC DC Specifications ............................................................... 4

ADC AC Specifications ............................................................... 5

Digital Specifications ................................................................... 7

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 12

Equivalent Circuits ......................................................................... 15

Theory of Operation ...................................................................... 16

ADC Architecture ...................................................................... 16

Analog Input Considerations.................................................... 16

Voltage Reference ....................................................................... 18

Clock Input Considerations...................................................... 18

Power Dissipation and Standby Mode .................................... 19

Digital Outputs ........................................................................... 20

ADC Overrange (OR)................................................................ 20

Noise Shaping Requantizer ........................................................... 21

22% BW NSR Mode (55 MHz BW at 250 MSPS) ..................... 21

33% BW NSR Mode (>82 MHz BW at 250 MSPS) ............... 21

Serial Port Interface (SPI).............................................................. 23

Configuration Using the SPI..................................................... 23

Hardware Interface..................................................................... 23

SPI Accessible Features.............................................................. 24

Memory Map .................................................................................. 25

Reading the Memory Map Register Table............................... 25

Memory Map Register Table..................................................... 26

Memory Map Register Description ......................................... 28

Applications Information .............................................................. 29

Design Guidelines ...................................................................... 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

12/14—Rev. B to Rev. C

Changes to Features Section............................................................ 1

Changes to 33% BW NSR Mode (>82 MHz BW at 250 MSPS)

Section.............................................................................................. 21

Changes to Reading the Memory Map Register Table Section .... 25

Changes to Table 13........................................................................ 26

Change to Memory Map Register Description Section............. 28

7/14—Rev. A to Rev. B

Changes to Features Section and Figure 1..................................... 1

Changes to Full Power Bandwidth Parameter, Table 2................ 6

Deleted Noise Bandwidth Parameter, Table 2............................... 6

11/12—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

7/11—Revision 0: Initial Version