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TPS548A20 데이터시트(PDF) 4 Page - Texas Instruments |
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TPS548A20 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 36 page 4 TPS548A20 SLUSC78A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Product Folder Links: TPS548A20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NAME NO. SW 6 I/O SW is the output switching terminal of the power converter. Connect this pin to the output inductor. 7 8 9 TRIP 25 I/O TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at TA = 25°C, 3000 ppm/°C current is sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for detailed OCP setting. VBST 4 P VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch. VDD 19 P Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V. VIN 15 P VIN is the conversion power-supply input pins. 16 17 VREG 20 O VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver. VO 24 I VOUT voltage input to the controller. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground terminal. (3) Voltage values are with respect to the SW terminal. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage range(2) EN –0.3 7.7 V SW DC –3 25 Transient < 10 ns –5 27 VBST –0.3 31 VBST(3) –0.3 6 VBST when transient < 10 ns 33 VDD –0.3 28 VIN –0.3 25 FB, MODE, VO –0.3 6 Output voltage range PGOOD –0.3 7.7 V TRIP, VREG –0.3 6 Junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 |
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