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UC1825A-SP 데이터시트(PDF) 10 Page - Texas Instruments |
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UC1825A-SP 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 39 page UDG-95108 0 0.1 0.2 0.3 0.8 0.5 0.6 0.7 0.9 0.4 0 0.5 1 1.5 2 2.5 3 1 Output Current (A) 25°C –55°C UDG-95106 VCC OUT PGND UVLO 50 k 250 A Q3 Q2 Q4 Q1 UDG-96106 Fault 5 V 1.2 V 1.2 V 0.2 V On Off PWM VSS UC1825A-SP SLUS873B – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Feature Description (continued) Figure 4. Soft-Start and Fault Waveforms 8.3.3 Active Low Outputs During UVLO The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate (see Figure 5 and Figure 6). Figure 5. Output Voltage vs Output Current Figure 6. Output V And I During UVLO 10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: UC1825A-SP |
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유사한 설명 - UC1825A-SP_15 |
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