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TDC7200PW 데이터시트(PDF) 5 Page - Texas Instruments |
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TDC7200PW 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 50 page 5 TDC7200 www.ti.com SNAS647D – FEBRUARY 2015 – REVISED MARCH 2016 Product Folder Links: TDC7200 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (3) All voltages are with respect to ground, unless otherwise specified. 7 Specifications 7.1 Absolute Maximum Ratings TA = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted). (1) (2) (3) MIN MAX UNIT VDD Supply voltage –0.3 3.9 V VI Terminal input voltage –0.3 VDD+0.3 V VDIFF_IN |Voltage differential| between any two input terminals 3.9 V VIN_GND_V DD |Voltage differential| between any input terminal and GND or VDD 3.9 V II Input current at any pin –5 5 mA TA Ambient temperature -40 125 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22- C101(2) ±250 (1) Specified by design. 7.3 Recommended Operating Conditions TA = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted). MIN NOM MAX UNIT VDD Supply voltage 2 3.6 V VI Terminal voltage 0 VDD V VIH Voltage input high 0.7 × VDD 3.6 V VIL Voltage input low 0 0.3 × VDD V FCALIB_CLK Frequency (Reference/Calibration Clock) 1 (1) 8 16 MHz DUTYCLOCK Input clock duty cycle 50% TIMING REQUIREMENTS: Measurement Mode 1 (1) T1STARTSTOP_Min Minimum Time between Start and Stop Signal 12 ns T1STOPSTOP_Min Minimum Time between 2 Stop Signals 67 ns T1STARTSTOP_Max Maximum time bet. Start and Stop Signal 500 ns T1STOPSTOP_Max Maximum time bet. Start and last Stop Signal 500 ns TIMING REQUIREMENTS: Measurement 2 (1) T2STARTSTOP_Min Minimum Time between Start and Stop Signal 2×tCLOCK s T2STOPSTOP_Min Minimum Time between 2 Stop Signals 2×tCLOCK s T2STARTSTOP_Max Maximum time bet. Start and Stop Signal (216-2)×tCLOCK s T2STOPSTOP_Max Maximum. time bet. Start and last Stop Signal (216-2)×tCLOCK s TIMING REQUIREMENTS: ENABLE INPUT TREN Rise Time for Enable Signal (20%-80%) 1 to 100 ns TFEN Fall Time for Enable Signal (20%-80%) 1 to 100 ns |
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