2B1

1B1

2A

1A

S0

S1

1OE

2OE

1B2

1B3

1B4

2B2

2B3

2B4

SW

SW

SW

SW

SW

SW

SW

SW

7

9

14

2

1

15

6

5

4

3

10

11

12

13

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SN74CBTLV3253

SCDS039I – DECEMBER 1997 – REVISED SEPTEMBER 2015

SN74CBTLV3253 Low-Voltage Dual 1-of-4 FET Multiplexer/Demultiplexer

1 Features

3 Description

The SN74CBTLV3253 device is a dual 1-of-4 high-

1

•

Functionally Equivalent to QS3253

speed FET multiplexer and demultiplexer. The low

•

5-

Ω Switch Connection Between Two Ports

ON-state resistance of the switch allows connections

•

Rail-to-Rail Switching on Data I/O Ports

to be made with minimal propagation delay.

•

The select (S0, S1) inputs control the data flow. The

•

Latch-Up Performance Exceeds 100 mA Per

FET multiplexers/demultiplexers are disabled when

JESD 78, Class II

the associated output-enable (OE) input is high.

The SN74CBTLV3253 device is fully specified for

2 Applications

feature ensures that damaging current will not

•

Video Broadcasting: IP-Based Multi-Format

backflow through the device when it is powered

Transcoders

down. The device has isolation during power off.

•

Video Communications Systems

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74CBTLV3253D

SOIC (16)

9.90 mm × 3.90 mm

SN74CBTLV3253DBQ

SSOP (16)

4.90 mm × 3.90 mm

SN74CBTLV3253DGV

TVSOP (16)

3.60 mm × 4.40 mm

SN74CBTLV3253RGY

VQFN (16)

4.00 mm × 3.50 mm

SN74CBTLV3253PW

TSSOP (16)

5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.