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ADV3228-EVALZ 데이터시트(PDF) 5 Page - Analog Devices |
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ADV3228-EVALZ 데이터시트(HTML) 5 Page - Analog Devices |
5 / 24 page Data Sheet ADV3228/ADV3229 Rev. A | Page 5 of 24 TIMING CHARACTERISTICS (SERIAL) Table 2. Parameter Symbol Min Typ Max Unit Serial Data Setup Time t1 10 ns CLK Pulse Width t2 10 ns Serial Data Hold Time t3 10 ns CLK Pulse Separation, Serial Mode t4 10 ns CLK to UPDATE Delay t5 10 ns UPDATE Pulse Width t6 10 ns CLK to DATAOUT Valid, Serial Mode t7 50 ns Propagation Delay, UPDATE to Switch On or Off 20 ns Data Load Time, CLK = 5 MHz, Serial Mode 8 µs CLK, UPDATE Rise and Fall Times 50 ns RESET Time 30 ns Timing Diagram—Serial Mode LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE 1 0 1 0 DATAIN CLK 1 = LATCHED 0 = TRANSPARENT DATAOUT OUT07 (D3) OUT07 (RESERVED) OUT00 (D0) TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t7 t1 t3 t6 t2 t4 t5 UPDATE Figure 2. Timing Diagram, Serial Mode LOGIC LEVELS Table 3. Logic Levels VIH VIL VOH VOL IIH IIL IIH IIL IOH IOL RESET, SER/PAR, CLK, DATA IN, CE, UPDATE RESET, SER/PAR, CLK, DATA IN, CE, UPDATE DATA OUT DATA OUT SER/PAR, CLK, DATA IN, CE, UPDATE SER/PAR, CLK, DATA IN, CE, UPDATE RESET RESET DATA OUT DATA OUT 2.0 V min 0.8 V max 2.4 V min 0.4 V max 2 µA max 2 µA max 2 µA max 300 µA max 3 mA min 1 mA min |
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