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APW8855 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 28 Page - Anpec Electronics Coropration

๋ถ€ํ’ˆ๋ช… APW8855
์ƒ์„ธ๋‚ด์šฉ  High Current, High Frequency 7 Outputs Voltage Regulator and Power Management IC for High Performance Tablet and Ultra Notebook Applications
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์ œ์กฐ์‚ฌ  ANPEC [Anpec Electronics Coropration]
ํ™ˆํŽ˜์ด์ง€  http://www.anpec.com.tw
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APW8855 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 28 Page - Anpec Electronics Coropration

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Copyright
ยฉ ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
APW8855
www.anpec.com.tw
28
14.6 VR5 Register Table
Address
0 x09
Field Name
VDDP_ ALW DAC [7: 0]
Da ta B it
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
V DDP _ALW_VS EL
Re ad/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On Defaul t
0
0
1
0
1
1
1
0
Bit Na me
Bit De finition
VDDP_A LW_V SEL
00 h : shutdown
01 h : VR5 Voltage = 50 0mV.
02 h : VR5 Voltage = 51 0mV.
03 h : VR5 Voltage = 52 0mV.
โ€ฆ
2e h : VR5 Voltage = 95 0mV (De fa ult)
โ€ฆ.
65 h : VR5 Voltage = 15 00mV.
66 h~ffh : Reserved
Addres s
0x 0A
Fie ld Na me
V DDP _ALW CO NTROL [7:0]
Data B it
D7
D6
D5
D4
D3
D2
D1
D0
Bit Na me
VDDP_ ALW_S LEW
V DDP _ALW_FSW
_SE L
VDDP_AL
W__ SEL
V DDP _AL
W__ EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Po wer O n De fa ult
Reserved
0
0
1
0
0
0
Bit Name
Bit Definition
VDDP_ ALW_E N
0: V R5 o ff (De fau lt)
1: V R4 o n
VDDP_ ALW_S EL
0: V R5 o n/off i s controlle d by CTL, an d o utput voltage is control by VDDP_ ALW_ GPIO. (Defa ult)
1: V R5 o n/off i s controlle d by VDDP_A LW_E N State a nd output vo ltag e i s control by
VDDP_A LW_V SEL.
VDDP_ ALW_ FSW _SEL
00 : FSW = 0.3MHz at PWM mod e.
01 : FSW = 0.6MHz at PWM mod e.
10 : FSW = 0.5MHz at PWM mod e. (Defau lt)
11 : FSW = 0.8MHz a t PWM mode.
VDDP_ ALW_S LEW
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s


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