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APW8855 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 33 Page - Anpec Electronics Coropration

๋ถ€ํ’ˆ๋ช… APW8855
์ƒ์„ธ๋‚ด์šฉ  High Current, High Frequency 7 Outputs Voltage Regulator and Power Management IC for High Performance Tablet and Ultra Notebook Applications
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์ œ์กฐ์‚ฌ  ANPEC [Anpec Electronics Coropration]
ํ™ˆํŽ˜์ด์ง€  http://www.anpec.com.tw
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APW8855 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 33 Page - Anpec Electronics Coropration

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Copyright
ยฉ ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
APW8855
www.anpec.com.tw
33
Protocol
Reads from PMIC registers follow the
โ€œcombined protocolโ€ as described in the I2C specification, in which the first byte
written is the register offset to be read, and the first byte read (after a repeat START condition) is the data from that
register offset. See the figures below for details. The following diagrams capture the different high-speed and fast-
speed transaction format/protocol.
15.2 I2C Function Description(Cont.)
Master to Slave
Slave to Master
S
7bit Slave
Address
A
8bit Address
8bit Data
A
R/W
P
โ€˜0โ€™
7'h6E
A
A= Acknowledge ( SDA LOW )
A=
Not Acknowledge
( SDA HIGH )
S= START Condition
P= STOP Condition
Reg. Address
Reg. Data
Figure 1. I2C Fast Speed / Fast Speed Plus Single Byte Write
Master to Slave
Slave to Master
S
7bit Slave
Address
A
8bit Reg.
Address
8bit Data
A
R/W
Reg. First Byte
Data
โ€˜0โ€™
8bit Data
A
Reg. Last Byte
Data
P
A
A= Acknowledge ( SDA LOW )
A=
Not Acknowledge
( SDA HIGH )
S= START Condition
P= STOP Condition
7'h 6E
Figure 2. I2C Fast Speed / Fast Speed Plus Multiple Byte Write
Figure 3. I2C Fast Speed / Fast Speed Plus Single Byte Read
Master to Slave
Slave to Master
S
7bit Slave
Address
A
8bit Address
A
R/W
Reg. Address
โ€˜0โ€™
Sr
7bit Slave
Address
7'h 6E
8bit Data
P
Reg. Data
A
A
R/W
โ€˜1โ€™
A= Acknowledge ( SDA LOW )
A=
Not Acknowledge
( SDA HIGH )
P= STOP Condition
S= START Condition
Sr=
Repeated START Condition
7'h 6E


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