AD7770 datasheet(10/94 Pages) AD

부품명	AD7770

상세설명	8-Channel, 24-Bit, Simultaneous Sampling ADC

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AD7770

Data Sheet

Rev. A | Page 10 of 94

SPI TIMING CHARACTERISTISTICS

AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;

IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,

unless otherwise noted.

Table 3.

Parameter

Description2

Test Conditions/Comments

Min

Typ

Max

Unit

t12

SCLK period

50:50

30

MHz

t13

SCLK low time

7

ns

t14

SCLK high time

7

ns

t15

SCLK rising edge to CS falling edge

10

ns

t16

CS falling edge to SCLK rising edge

10

ns

t17

SCLK rising edge to CS rising edge

10

ns

t18

CS rising edge to SCLK rising edge

10

ns

t19

Minimum CS high time

10

ns

t20

SDI setup time

5

ns

t21

SDI hold time

5

ns

t22A

CS falling edge to SDO enable (SPI = Mode 0)

30

ns

t22B

SCLK falling edge to SDO enable (SPI = Mode 1)

49

ns

t23

SDO setup time

10

ns

t24

SDO hold time

10

ns

t25

CS rising edge to SDO disable

30

ns

1

AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.

2

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.

CS

SCLK

MSB

MSB – 1

LSB + 1

LSB

SDI

MSB

MSB – 1

LSB + 1

LSB

SDO

t15

t16

t13

t14

t20

t22A

t21

t24

t23

t22B

t12

t19

t17

t18

t25

Figure 3. SPI Control Interface Timing Diagram

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