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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD7768-4BSTZ-RL7 데이터시트(PDF) 3 Page - Analog Devices |
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AD7768-4BSTZ-RL7 데이터시트(HTML) 3 Page - Analog Devices |
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3 / 99 page  Data Sheet AD7768/AD7768-4 Rev. A | Page 3 of 99 Digital Filter RAM Built In Self Test (BIST) Register ............92 Status Register..............................................................................92 Revision Identification Register................................................93 GPIO Control Register...............................................................93 GPIO Write Data Register .........................................................94 GPIO Read Data Register ..........................................................94 Analog Input Precharge Buffer Enable Register Channel 0 And Channel 1.............................................................................94 Analog Input Precharge Buffer Enable Register Channel 2 And Channel 3.............................................................................95 Positive Reference Precharge Buffer Enable Register.............95 Negative Reference Precharge Buffer Enable Register...........95 Offset Registers............................................................................96 Gain Registers..............................................................................96 Sync Phase Offset Registers.......................................................96 ADC Diagnostic Receive Select Register.................................96 ADC Diagnostic Control Register............................................97 Modulator Delay Control Register ...........................................97 Chopping Control Register........................................................98 Outline Dimensions........................................................................99 Ordering Guide ...........................................................................99 REVISION HISTORY 3/16—Rev. 0 to Rev. A Added AD7768-4 ...............................................................Universal Changed Precharge Analog Input Reference to Analog Input Precharge........................................................................ Throughout Changes to General Description Section .......................................5 Changes to Table 1 ............................................................................6 Changes to Table 2 ..........................................................................12 Changes to Table 3 and t30 Parameter, Table 4.............................16 Changes to Table 5 ..........................................................................17 Changes to t30 Parameter, Table 6 and Figure 2...........................18 Changes to Figure 4 and Figure 7..................................................19 Changes to Figure 8 and Figure 9..................................................20 Changes to Figure 10 and Table 9 .................................................22 Added Figure 11 and Table 10; Renumbered Sequentially........26 Changes to Typical Performance Characteristics Section .........30 Changes to Theory of Operation Section and Clocking, Sampling Tree, and Power Scaling Section..................................41 Changes to Table 11 ........................................................................42 Added Example of Power vs. Noise Performance Optimization Section and Clocking Out the ADC Conversion Results (DCLK) Section...............................................................................42 Changes to Applications Information Section and Figure 73 ...44 Changes to Table 14 and Power Supplies Section .......................45 Moved 1.8 V IOVDD Operation Section.....................................46 Changes to Figure 75, Analog Supply Internal Connectivity Section, and Pin Control Section..................................................46 Added Figure 76 ..............................................................................47 Changes to Channel Standby Section and Accessing the ADC Register Map Section ......................................................................49 Added Table 22 ................................................................................49 Changes to Channel Configuration Section................................50 Changes to Channel Modes Section, Reset over SPI Control Interface Section, Sleep Mode Section, and Channel Standby Section ..............................................................................................51 Changes to MCLK Source Selection Section, Interface Configuration Section, and ADC Synchronization over SPI Section ..............................................................................................52 Added Figure 81 ..............................................................................52 Changes to RAM Built In Self Test Section .................................53 Changes to Analog Inputs Section and Figure 85.......................55 Added Figure 86 ..............................................................................55 Added Table 27................................................................................56 Changes to VCM Section, Reference Input Section, and Digital Filtering Section ..............................................................................56 Changes to Figure 87, Figure 88, and Figure 89..........................57 Changes to Antialiasing Section and Modulator Sampling Frequency Section...........................................................................58 Changes to Modulator Chopping Frequency Section and Table 29, and Modulator Saturation Point Section,....................59 Changes to Sync Phase Offset Adjustment Section....................60 Changes to Setting the Format of Data Output Section ............61 Added Table 32 and Figure 93.......................................................61 Changes to Figure 94 Caption and ADC Conversion Output: Header and Data Section ...............................................................62 Changes to Data Interface: Standard Conversion Operation Section ..............................................................................................63 Changes to Figure 99 ......................................................................64 Added Figure 100............................................................................64 Added Figure 101............................................................................65 Changes to Daisy-Chaining Section and Figure 104..................66 Added Figure 105............................................................................67 Changes to CRC Check on Data Interface Section ....................68 Changes to Table 35 ........................................................................69 Changes to Table 36 ........................................................................70 Changes to GPIO Functionality Section and Figure 108...........71 Added Figure 109............................................................................71 Changes to AD7768 Register Map Details (SPI Control) Section and Table 37 .....................................................................................72 Changes to Channel Standby Register Section ...........................74 Changes to Table 42 and Table 43.................................................76 Changes to Table 44 ........................................................................77 Changes to Table 45 and Table 46.................................................78 Changes to Table 49 ........................................................................79 Changes to Table 61 ........................................................................85 Added AD7768-4 Register Map Details (SPI Control) Section and Table 63......................................................................................................86 |
유사한 부품 번호 - AD7768-4BSTZ-RL7 |
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유사한 설명 - AD7768-4BSTZ-RL7 |
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