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FM24V01A-G 데이터시트(PDF) 4 Page - Cypress Semiconductor

부품명 FM24V01A-G
상세설명  128-Kbit (16K 횞 8) Serial (I2C) F-RAM
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24V01A-G 데이터시트(HTML) 4 Page - Cypress Semiconductor

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FM24V01A
Document Number: 001-90869 Rev. *H
Page 4 of 19
Functional Overview
The FM24V01A is a serial F-RAM memory. The memory array is
logically organized as 16,384 × 8 bits and is accessed using a
two-wire (I2C) interface. The functional operation of the F-RAM
is similar to serial EEPROM. The major difference between the
FM24V01A and a serial EEPROM with the same pinout is the
F-RAM's superior write performance, high endurance, and low
power consumption.
Memory Architecture
When accessing the FM24V01A, the user addresses 16K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the two-wire
protocol, which includes a slave address (to distinguish other
non-memory devices) and a two-byte address. The upper 2 bits
of the address range are 'don't care' values. The complete
address of 14 bits specifies each byte address uniquely.
The access time for the memory operation is essentially zero,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the two-wire bus. Unlike
a serial EEPROM, it is not necessary to poll the device for a
ready condition because writes occur at bus speed. By the time
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
Memory Operation on page 6.
Two-wire Interface
The FM24V01A employs a bidirectional two-wire bus protocol
using few pins or board space. Figure 2 illustrates a typical
system configuration using the FM24V01A in a microcon-
troller-based system. The two-wire bus is familiar to many users
but is described in this section.
By convention, any device that is sending data to the bus is the
transmitter while the target device for this data is the receiver.
The device that is controlling the bus is the master. The master
is responsible for generating the clock signal for all operations.
Any device on the bus that is being controlled is a slave. The
FM24V01A is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge. Figure 3 and Figure 4 on page 5 illus-
trate the signal conditions that specify the four states. Detailed
timing diagrams are shown in the electrical specifications
section.
The FM24V01A does not meet the NXP I2C specification in the
Fast-mode Plus (Fm+, 1 MHz) for IOL and in the High Speed
Mode (Hs-mode, 3.4 MHz) for Vhys. Refer to the DC Electrical
Characteristics table for more details.
STOP Condition (P)
A STOP condition is indicated when the bus master drives SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24V01A should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of the SDA (not a
memory read) to assert a STOP condition.
START Condition (S)
A START condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the START condition will ready
the FM24V01A for a new operation.
Figure 2. System Configuration Using Serial (I2C) F-RAM
SDA
SCL
DD
A0
A0
A0
A1
A1
A1
SCL
SCL
SCL
SDA
SDA
SDA
WP
WP
WP
#0
#1
#7
A2
A2
A2
Microcontroller
V
DD
V
DD
V
FM24V01A
FM24V01A
FM24V01A
RPmin = (VDD - VOLmax) / IOL
RPmax = tr / (0.8473 * Cb)


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