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MC145200 데이터시트(PDF) 4 Page - Motorola, Inc |
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MC145200 데이터시트(HTML) 4 Page - Motorola, Inc |
4 / 23 page MC145200 •MC145201 MOTOROLA 4 ANALOG CHARACTERISTICS—CURRENT SOURCE/SINK OUTPUT—PDout (Iout ≤ 2 mA, VDD = VCC = 4.5 to 5.5 V, VDD ≤ VPD. Voltages Referenced to GND) Parameter Test Condition VPD Guaranteed Limit Unit Maximum Source Current Variation MC145200: Vout = 0.5 × VPD 8.0 ± 20 % 9.5 ± 20 MC145201: Vout = 0.5 × VPD 4.5 ± 20 % 5.5 ± 20 Maximum Sink–vs–Source Mismatch (Note 3) MC145200: Vout = 0.5 × VPD 8.0 12 % 9.5 12 MC145201: Vout = 0.5 × VPD 4.5 12 % 5.5 12 Output Voltage Range (Note 3) MC145200: Iout variation ≤ 20% 8.0 0.5 to 7.5 V 9.5 0.5 to 9.0 MC145201: Iout variation ≤ 20% 4.5 0.5 to 4.0 V 5.5 0.5 to 5.0 NOTES: 1. Percentages calculated using the following formula: (Maximum Value – Minimum Value) / Maximum Value. 2. See Rx Pin Description for external resistor values. 3. This parameter is guaranteed for a given temperature within – 40 to + 85 °C. AC INTERFACE CHARACTERISTICS (VDD = 4.5 to 5.5 V, TA = – 40 to + 85°C, CL = 50 pF, Input tr = tf = 10 ns; MC145200: VPD = 8.0 to 9.5 V; MC145201: VPD = 4.5 to 5.5 V with VDD ≤ VPD) Symbol Parameter Figure No. Guaranteed Limit Unit fclk Serial Data Clock Frequency (Note: Refer to Clock tw below) 1 dc to 4.0 MHz tPLH, tPHL Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out) 1, 5 105 ns tPLH, tPHL Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port) 2, 5 100 ns tPZL, tPLZ Maximum Propagation Delay, ENB to OUTPUT B 2, 6 120 ns tTLH, tTHL Maximum Output Transition Time, OUTPUT A and OUTPUT B; tTHLonly, on OUTPUT B 1, 5, 6 100 ns Cin Maximum Input Capacitance – Din, ENB, CLK, 10 pF TIMING REQUIREMENTS (VDD = 4.5 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated) Symbol Parameter Figure No. Guaranteed Limit Unit tsu, th Minimum Setup and Hold Times, Din vs CLK 3 20 ns tsu, th, trec Minimum Setup, Hold and Recovery Times, ENB vs CLK 4 100 ns tw Minimum Pulse Width, ENB 4 * cycles tw Minimum Pulse Width, CLK 1 125 ns tr, tf Maximum Input Rise and Fall Times, CLK 1 100 µs * The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater. |
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