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IRL3103S 데이터시트(PDF) 5 Page - International Rectifier

부품명 IRL3103S
상세설명  5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRONOUS,ADJUSTABLE LDO AND 200mA ON-BOARD LDO
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제조업체  IRF [International Rectifier]
홈페이지  http://www.irf.com
Logo IRF - International Rectifier

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IRU3007
5
Rev. 2.1
08/20/02
www.irf.com
This pin provides the feedback for the non-synchronous switching regulator. A resistor
divider is connected from this pin to VOUT2 and ground that sets the output voltage. The
value of the resistor connected from VOUT2 to Fb2 must be less than 100
V.
5V supply voltage. A high frequency capacitor (0.1 to 1
mF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft-start for the 2 switching regulators. An internal resistor charges
an external capacitor that is connected from 5V supply to this pin which ramps up the
outputs of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft-Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if any of
the switcher outputs exceed the OVP trip point, the Fault pin switches to 12V and the
soft-start cap is discharged. If the Fault pin is to be connected to any external circuitry,
it needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator that its output is VOUT4.
This pin is connected to the output of the I/O switching regulator. It is an input that
provides sensing for the Under/Over-voltage circuitry for the I/O supply as well as the
power for the internal LDO regulator.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Gate3.
No connection.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to VOUT1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from VOUT1 to Fb1 must be less than 100
V.
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1
mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high-side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1
mF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free
operation.
PIN#
PIN SYMBOL
PIN DESCRIPTION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Fb2
V5
SS
Fault / Rt
Fb4
VSEN2
VOUT4
Gnd
Gate3
Fb3
NC
Fb1
VSEN1
OCSet1
PGnd
LGate1
Phase1
UGate1
V12


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