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DAC1231LCJ-1 데이터시트(PDF) 3 Page - National Semiconductor (TI) |
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DAC1231LCJ-1 데이터시트(HTML) 3 Page - National Semiconductor (TI) |
3 / 18 page Electrical Characteristics (Continued) VREF e 10000 VDC VCC e 114 VDC to 1575 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 13) all other limits TA e TJ e 25 C See Typ Tested Design Symbol Parameter Conditions Note (Note 10) Limit Limit Units (Note 5) (Note 6) AC CHARACTERISTICS ts Current Setting Time VIL e 0V VIH e 5V 10 m s tW Write and XFER VIL e 0V VIH e 5V 8 50 320 Pulse Width Min 320 tDS Data Setup Time Min VIL e 0V VIH e 5V 70 320 320 tDH Data Hold Time Min VIL e 0V VIH e 5V 30 90 ns 90 tCS Control Setup Time Min VIL e 0V VIH e 5V 60 320 320 tCH Control Hold Time Min VIL e 0V VIH e 5V 0 10 Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking Note 4 Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier The linearity error is degraded by approximately VOSdVREF For example if VREFe10V thena1mV offset VOS onIOUT1 or IOUT2 will introduce an additional 001% linearity error Note 5 Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 6 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels Guaranteed for VCC e 114V to 1575V and VREF eb10V to a10V Note 7 The unit FSR stands for full-scale range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part The Linearity Error specification of the DAC1208 is 0012% of FSR(max) This guarantees that after performing a zero and full-scale adjustment the plot of the 4096 analog voltage outputs will each be within 0012% c VREF of a straight line which passes through zero and full-scale The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs of very small percentage values typical of higher accuracy converters In this instance 1 ppm of FSReVREF 106 is the conversion factor to provide an actual output voltage quantity For example the gain error tempco spec of g6 ppm of FS C represents a worst-case full-scale gain error change with temperature from b 40 Cto a85 Cof g(6)(VREF 106)(125 C) or g075 (10b3)VREF which is g0075% of VREF Note 8 This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns A typical part will operate with tW of only 100 ns The entire write pulse must occur within the valid data interval for the specified tW tDS tDH and tS to apply Note 9 To achieve this low feedthrough in the D package the user must ground the metal lid If the lid is left floating the feedthrough is typically 6 mV Note 10 Typicals are at 25 C and represent the most likely parametric norm Note 11 A 10 nA leakage current with RFbe20k and VREFe10V corresponds to a zero error of (10c10b9c20c103)c100% 10V or 0002% of FS Note 12 Human body model 100 pF discharged through a 15 kX resistor Note 13 Tested limit for b1 suffix parts applies only at 25 C Connection Diagrams Dual-In-Line Package Dual-In-Line Package TLH5690 – 2 See Ordering Information 3 |
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