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CD74HC138M96 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Texas Instruments

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๋ถ€ํ’ˆ๋ช… CD74HC138M96
์ƒ์„ธ๋‚ด์šฉ  High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting
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CD74HC138M96 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Texas Instruments

 
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Enable to Output
HC/HCT138
tPLH, tPHL CL = 50pF
2
-
-
150
-
190
-
265
ns
4.5
-
-
30
-
38
-
53
ns
6
-
-
26
-
33
-
45
ns
Output Transition Time
(Figure 1)
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Power Dissipation
Capacitance (Notes 3, 4)
CPD
CL = 15pF
5
-
67
-
-
-
-
-
pF
Input Capacitance
CIN
-
-
-
-
10
-
10
-
10
pF
HCT TYPES
Propagation Delay
Address to Output
tPLH, tPHL CL = 50pF
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
Enable to Output
HC/HCT138
tPLH, tPHL CL = 50pF
4.5
-
-
35
-
44
-
53
ns
Enable to Output
HC/HCT238
tPLH, tPHL CL = 15pF
4.5
-
-
40
-
50
-
60
ns
Output Transition Time
(Figure 2)
tTLH, tTHL CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Power Dissipation
Capacitance (Notes 3, 4)
CPD
CL = 15pF
5
-
67
-
-
-
-
-
pF
Input Capacitance
CIN
-
-
-
-
10
-
10
-
10
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC
2 f
i (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Speci๏ฌcations Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO
85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238


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