Rev: 1.04a 10/2002

1/18

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS72116ATP/J/T/U

128K x 16

2Mb Asynchronous SRAM

7, 8, 10, 12 ns

SOJ, TSOP, FP-BGA, TQFP

Commercial Temp

Industrial Temp

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 145/125/100/85 mA at

minimum cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 44-pin SOJ package

TP: 400 mil, 44-pin TSOP Type II package

T: 10 mm x 10 mm, 44-pin TQFP

U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

Description

The GS72116A is a high speed CMOS Static RAM organized

as 131,072 words by 16 bits. Static design eliminates the need

for external clocks or timing strobes. The GS operates on a sin-

gle 3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS72116A is available in a 6 mm x 8 mm

Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as

well as in 400 mil SOJ and 400 mil TSOP Type-II packages.

Pin Descriptions

SOJ 128K x 16-Pin Configuration

Package J

Symbol

Description

Address input

Data input/output

CE

Chip enable input

LB

Lower byte enable input

(DQ1 to DQ8)

UB

Upper byte enable input

(DQ9 to DQ16)

WE

Write enable input

OE

Output enable input

+3.3 V power supply

Ground

NC

No connect

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CE

DQ6

DQ7

WE

OE

UB

LB

NC

Top view

21

22

24

23

44-pin

SOJ

NC