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ADC08500 데이터시트(PDF) 7 Page - Texas Instruments

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부품명 ADC08500
상세설명  High Performance, Low Power 8-Bit, 500 MSPS A/D Converter
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VDR
DR GND
+
-
+
-
ADC08500
www.ti.com
SNAS373E – MAY 2007 – REVISED APRIL 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Out Of Range output. A differential high at these pins indicates
that the differential input is out of range (outside the range
79
OR+
±VIN/2 as programmed by the FSR pin in non-extended control
80
OR-
mode or the Input Full-Scale Voltage Adjust register setting in
the extended control mode).
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
82
DCLK+
signal. This signal is at 1/2 the input clock rate in SDR mode
81
DCLK-
and at 1/4 the input clock rate in the DDR mode. The DCLK
outputs are not active during a calibration cycle, therefore this is
not recommended as a system clock.
2, 5, 8, 13,
16, 17, 20,
VA
Analog power supply pins. Bypass these pins to ground.
25, 28, 33,
128
40, 51 ,62,
Output Driver power supply pins. Bypass these pins to DR
73, 88, 99,
VDR
GND.
110, 121
1, 6, 9, 12,
21, 24, 27,
GND
Ground return for VA.
41
42, 53, 64,
74, 87, 97,
DR GND
Ground return for VDR.
108, 119
22, 23, 29,
36–39,
43–50, 52,
54–61, 63,
NC
No Connection. Make no connection to these pins.
65–72,
75–78, 98,
109, 120
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2013, Texas Instruments Incorporated
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