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ADC081000 데이터시트(PDF) 4 Page - Texas Instruments

부품명 ADC081000
상세설명  High Performance, Low Power 8-Bit, 1 GSPS A/D Converter
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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ADC081000 데이터시트(HTML) 4 Page - Texas Instruments

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50k
VA
AGND
11
VA
AGND
10
50k
Control from DC_Coup
VCMO
100
VA
AGND
18
VA
AGND
19
100
VBIAS
50k
50k
GND
VA
ADC081000
SNAS209G – FEBRUARY 2004 – REVISED MAY 2013
www.ti.com
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude set. Tie this pin high for normal
differential output amplitude. Ground this pin for a reduced
3
OutV
differential output amplitude and reduced power consumption.
See The LVDS Outputs.
Output Edge Select. Sets the edge of the DCLK+ (pin 82) at
which the output data transitions. The output transitions with the
4
OutEdge
DCLK+ rising edge when this pin is high or on the falling edge
when this pin is low. See Output Edge Synchronization.
DC Coupling select. When this pin is high, the VIN+ and VIN-
analog inputs are d.c. coupled and the input common mode
voltage should equal the VCMO (pin 7) output voltage. When this
14
DC_Coup
pin is low, the analog input pins are internally biased and the input
signal should be a.c. coupled to the analog input pins. See THE
ANALOG INPUT.
Power Down Pin. A logic high on this pin puts the ADC into the
26
PD
Power Down mode. A logic low on this pin allows normal
operation.
Calibration. A minimum 10 clock cycles low followed by a
30
CAL
minimum of 10 clock cycles high on this pin will initiate the self
calibration sequence. See Self-Calibration.
Full scale Range Select. With a logic low on this pin, the full-scale
35
FSR
differential input is 600 mVP-P. With a logic high on this pin, the
full-scale differential input is 800 mVP-P. See The Analog Inputs.
Calibration Delay. This sets the number of clock cycles after
127
CalDly
power up before calibration begins. See Self-Calibration.
Clock input pins for the ADC. The differential clock signal must be
18
CLK+
a.c. coupled to these pins. The input signal is sampled on the
19
CLK–
falling edge of CLK+.
11
VIN+
Analog Signal Differential Inputs to the ADC.
10
VIN-
4
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Product Folder Links: ADC081000


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