 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ADC121S655 데이터시트(PDF) 5 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADC121S655 데이터시트(HTML) 5 Page - Texas Instruments |
|
|
5 / 31 page  ADC121S655 www.ti.com SNAS402A – MAY 2007 – REVISED MARCH 2013 ADC121S655 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 3.2 to 8 MHz, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units(2) 4.5 V (min) VA Analog Supply Voltage 5.5 V (max) fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100 1.8 2.2 mA (max) kHz IVA Supply Current, Normal Mode (Normal)) (Operational) fSCLK = 3.2 MHz, fS = 200 kSPS, fIN = 100 1.4 mA kHz fSCLK = 8 MHz 32 µA (max) Supply Current, Power Down Mode IVA (PD) (CS high) fSCLK = 0 (1) 0.3 2 µA (max) fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100 9 mW kHz, VA = 5.0V PWR Power Consumption, Normal Mode (Normal)) (Operational) fSCLK = 3.2 MHz, fS = 200 kSPS, fIN = 100 7 mW kHz, VA = 5.0V fSCLK = 8 MHz, VA = 5.0V 200 µW PWR Power Consumption, Power Down (PD) Mode (CS high) fSCLK = 0, VA = 5.0V 1.5 µW See the Specification Definitions for the test PSRR Power Supply Rejection Ratio −85 dB condition AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency 16 8 MHz (min) fSCLK Minimum Clock Frequency 0.8 3.2 MHz (max) fS Maximum Sample Rate(3) 1000 500 kSPS (min) SCLK cycles 2.5 (min) tACQ Track/Hold Acquisition Time SCLK cycles 3.0 (max) tCONV Conversion Time 13 SCLK cycles tAD Aperture Delay See the Specification Definitions 6 ns (3) While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16. ADC121S655 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 3.2 MHz to 8 MHz, CL = 25 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units tCSH CS Hold Time after an SCLK rising edge 5 ns (min) tCSSU CS Setup Time prior to an SCLK rising edge 5 ns (min) tDH DOUT Hold time after an SCLK Falling edge 7 2.5 ns (min) tDA DOUT Access time after an SCLK Falling edge 18 22 ns (max) tDIS DOUT Disable Time after the rising edge of CS (2) 20 ns (max) tEN DOUT Enable Time after the falling edge of CS 8 20 ns (max) tCH SCLK High Time 25 ns (min) tCL SCLK Low Time 25 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns (1) Data sheet min/max specification limits are specified by design, test, or statistical analysis. (2) tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC121S655 |
유사한 부품 번호 - ADC121S655 |
|
유사한 설명 - ADC121S655 |
|
|
링크 URL |
| 개인정보취급방침 |
| ALLDATASHEET.CO.KR |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
