전자부품 데이터시트 검색엔진 |
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74AC11648NT 데이터시트(PDF) 6 Page - Texas Instruments |
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74AC11648NT 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 10 page 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3STATE OUTPUTS SCAS114 − MARCH 1990 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−6 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 0 40 0 40 MHz tw Pulse duration, CLK high or low 12.5 12.5 ns tsu Setup time, A or B before CLKAB ↑ or CLKBA↑ 6.5 6.5 ns th Hold time, A or B after CLKAB ↑ or CLKBA↑ 0 0 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 0 90 0 90 MHz tw Pulse duration, CLK high or low 5.6 5.6 ns tsu Setup time, A or B before CLKAB ↑ or CLKBA↑ 4.5 4.5 ns th Hold time, A or B after CLKAB ↑ or CLKBA↑ 1 1 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER FROM TO TA = 25°C MIN MAX UNIT PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX UNIT fmax 40 40 MHz tPLH A or B B or A 3 8.7 12.6 3 14.3 ns tPHL A or B B or A 3.8 9.3 14.4 3.8 15.9 ns tPZH OE A or B 5 11.1 17.2 5 19.4 ns tPZL OE A or B 5.2 12.8 20.5 5.2 23 ns tPHZ OE A or B 4.1 7.2 9.9 4.1 10.6 ns tPLZ OE A or B 3.7 6.5 9.1 3.7 9.7 ns tPLH CLKBA or CLKAB A or B 4.3 10.1 15.6 4.3 17.6 ns tPHL CLKBA or CLKAB A or B 5.2 11.5 17.6 5.2 19.4 ns tPLH SBA or SAB† A or B 3.7 9.1 14.1 3.7 15.8 ns tPHL SBA or SAB† (A or B high) A or B 4.5 10.3 15.9 4.5 17.4 ns tPLH SBA or SAB† A or B 3.2 8.6 13.6 3.2 15.3 ns tPHL SBA or SAB† (A or B low) A or B 4.6 10.3 15.6 4.6 17.1 ns tPZH DIR A or B 4.9 11.6 18.2 4.9 20.6 ns tPZL DIR A or B 5.2 14.2 21.6 5.2 24.3 ns tPHZ DIR A or B 3.8 7.1 10.1 3.8 10.9 ns † These parameters are measured with the internal output state of the storage register opposite to that of the bus input. |
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