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์ƒ์„ธ๋‚ด์šฉ  28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
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DESCRIPTION (CONTINUED)
74SSTUB32868A
SCAS846C โ€“ JULY 2007 โ€“ REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and
latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error
occurs on the clock cycle before the device enters the low
โˆ’power mode (LPM) and the QERR output is driven
low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity
check computation.
The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration
(when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low
or high level to configure the register in the desired mode.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time to enable the
differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32868A
must ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C
inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1)
and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs
are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1
inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1 is low, the
QERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control and when
driven low forces the Qn outputs low, and the QERR output high. If the chip-select control functionality is not
desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0
and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and
DCS1 only, then the CSGEN input should be pulled up to VCC through a pullup resistor.
The two VREF pins (A5 and AB5) are connected together internally by approximately 150 โ„ฆ. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
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Copyright ยฉ 2007โ€“2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A


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